Nios Isa Simulator
NIOS is a soft cpu core developed by Altera and designed to be synthesized into their FPGA parts.
The cpu is pipelined with 6 stages and comes in several flavors. The base cpu can run out of local ram. The highest end cpu can use DRAM and boot linux.
During several NIOS projects I found a needed a simple instruction set simulator, so I wrote one. The simulator is easily modified to act like various FPGA instantiation. One flavor of the simulator includes the mmu/tlb subsystem and will boot linux.
I also did some verilog simulator of the nios behavioral model using verilator. This required creating models for Altera's dual port ram and several other components. I used this jig to boot linux in simulation and watch various TLB interactions.